Jun Cao, A. Momtaz, K. Vakilian, M.M. Green, D. Chung, K. Jen, M. Caresosa, B. Tan, I. Fujimori, A. Hairapetian
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引用次数: 14
Abstract
A fully integrated OC-192 multi-rate (9.95Gb/s-10.71Gb/s) receiver uses standard 0.18/spl mu/m CMOS. The circuit consists of an input amplifier, CDR, 1:16 demux and 18 LVDS drivers. The chip exceeds SONET jitter tolerance spec by >100%. Recovered 10Gb/s clock jitter is <4mUl(rms). The input sensitivity is <50mV with 870mW at 1.8V.
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