Efficient Hardware Acceleration for Design Diversity Calculation to Mitigate Common Mode Failures

Abstract

This paper presents an FPGA-based hardware acceleration of the design diversity calculation to build robust redundant hardware systems against common model failures. We exploit the benefits of C-based VLSI design to generate a design pool of micro-architectures with unique characteristics from the same behavioral description. To identify the most diverse design pairs from this massive design pool, a computationally-intensive fault-injection based process is needed. Thus, in this work, we leverage the use of FPGAs to accelerate the design diversity calculation. Experimental results show an average of 2x speedup compared to a traditional software implementation. We also show that much higher speedups can be achieved when using larger FPGAs that can host a larger pool of designs.