An ultra-low power and area efficient 10 bit digital to analog converter architecture

Abstract

An ultra-low power and area efficient successive approximation register (SAR) analog-to-digital converter (ADC) is presented. To achieve ultra-low power performance, a digital-to-analog converter (DAC) architecture is proposed that combined a 4-bit thermometer coded and a 6-bit C-2C array to form a 10-bit DAC. Thereby, power consumption and area of the design are drastically reduced by virtue of lower switching activity and smaller size capacitor array. Add on to that, the architecture also has better linearity. The proposed 10-bit DAC is designed and simulated in a 0.18 μm CMOS process. Simulation results show that it only consumed 1.74 nW at 1.5 V power supply.