Hardware-accelerated pose estimation for embedded systems using Vivado HLS

J. Joseph, Tobias Winker, Kristian Ehlers, Christopher Blochwitz, Thilo Pionteck
{"title":"Hardware-accelerated pose estimation for embedded systems using Vivado HLS","authors":"J. Joseph, Tobias Winker, Kristian Ehlers, Christopher Blochwitz, Thilo Pionteck","doi":"10.1109/ReConFig.2016.7857173","DOIUrl":null,"url":null,"abstract":"The focus of this work is to facilitate pose estimation and, thus, gesture recognition for embedded systems, although these are tasks with high computational performance requirements. Therefore, an existing pose estimation algorithm is optimized for Xilinx High Level Synthesis (HLS). The resulting hardware acceleration cores are compared for different optimizations and, finally, we propose a hardware/software system design for a Xilinx Zynq Zedboard. Using this method, we achieve a speedup of 1.6 in comparison to a software solution on the ARM processor and, thus, facilitate hand tracking for embedded systems with low power consumption.","PeriodicalId":431909,"journal":{"name":"2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ReConFig.2016.7857173","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

The focus of this work is to facilitate pose estimation and, thus, gesture recognition for embedded systems, although these are tasks with high computational performance requirements. Therefore, an existing pose estimation algorithm is optimized for Xilinx High Level Synthesis (HLS). The resulting hardware acceleration cores are compared for different optimizations and, finally, we propose a hardware/software system design for a Xilinx Zynq Zedboard. Using this method, we achieve a speedup of 1.6 in comparison to a software solution on the ARM processor and, thus, facilitate hand tracking for embedded systems with low power consumption.
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基于Vivado HLS的嵌入式系统硬件加速姿态估计
这项工作的重点是促进姿态估计,从而促进嵌入式系统的手势识别,尽管这些任务具有很高的计算性能要求。因此,针对Xilinx High Level Synthesis (HLS),对现有的姿态估计算法进行了优化。最后,我们提出了Xilinx Zynq Zedboard的硬件/软件系统设计方案。使用这种方法,与ARM处理器上的软件解决方案相比,我们实现了1.6的加速,从而促进了低功耗嵌入式系统的手部跟踪。
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