{"title":"A 0.6V, 1.3GHz dynamic comparator with cross-coupled latches","authors":"B. Kuo, B. Chen, Chia-Ming Tsai","doi":"10.1109/VLSI-DAT.2015.7114523","DOIUrl":null,"url":null,"abstract":"This paper presents a sub-1V dynamic comparator with cross-coupled latches at multi-GHz operation. The low-voltage cross-coupled latches structure with a separated tail current can be used to optimize the speed and the offset in the latched stage, respectively. A high speed readout circuit is also proposed to further enhance the speed of the comparator. With BER=109, the comparator achieves 143fJ at 3.3GHz and a 0.9V supply, which decreases to only 49fJ at 1.3GHz and a 0.6V supply. Both measured results are based on the input differential voltage of only 4.2mV. The comparator is implemented in 65nm CMOS technology and the chip area of the core circuit occupies 265μm2.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Design, Automation and Test(VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT.2015.7114523","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
This paper presents a sub-1V dynamic comparator with cross-coupled latches at multi-GHz operation. The low-voltage cross-coupled latches structure with a separated tail current can be used to optimize the speed and the offset in the latched stage, respectively. A high speed readout circuit is also proposed to further enhance the speed of the comparator. With BER=109, the comparator achieves 143fJ at 3.3GHz and a 0.9V supply, which decreases to only 49fJ at 1.3GHz and a 0.6V supply. Both measured results are based on the input differential voltage of only 4.2mV. The comparator is implemented in 65nm CMOS technology and the chip area of the core circuit occupies 265μm2.
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