{"title":"A 0.5V high speed DRAM charge transfer sense amplifier","authors":"Hwang-Cherng Chow, Chaung-Lin Hsieh","doi":"10.1109/MWSCAS.2007.4488787","DOIUrl":null,"url":null,"abstract":"A new charge transfer sense amplifier scheme is proposed for high speed 0.5 V DRAMs. The combination of both cross-coupled structure and boost capacitance of the proposed sense amplifier leads to the maximum voltage difference between sense nodes and 40% faster operation than prior art circuits.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 50th Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2007.4488787","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A new charge transfer sense amplifier scheme is proposed for high speed 0.5 V DRAMs. The combination of both cross-coupled structure and boost capacitance of the proposed sense amplifier leads to the maximum voltage difference between sense nodes and 40% faster operation than prior art circuits.
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