Pub Date : 2007-12-01DOI: 10.1109/MWSCAS.2007.4488618
T. Uto, K. Ichiwara, M. Ikeharat, K. Ohue
In this paper, a novel design method of regular cosine-modulated filter banks (CMFB's) have been presented for image coding. After introducing a regularity constraint on lattice parameters of a prototype filter in paraunitary (PU) CMFB's, we derive a regularity condition for perfect reconstruction (PR) CMFB's. Finally, we design regular 8-channel 32-length PUCMFB and PRCMFB by a unconstrained optimization of residual lattice parameters, and several simulation results for test images are shown for evaluating the proposed image coder based on the CMFB's with one degree of regularity.
{"title":"Image coding based on regular cosine-modulated filter banks","authors":"T. Uto, K. Ichiwara, M. Ikeharat, K. Ohue","doi":"10.1109/MWSCAS.2007.4488618","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488618","url":null,"abstract":"In this paper, a novel design method of regular cosine-modulated filter banks (CMFB's) have been presented for image coding. After introducing a regularity constraint on lattice parameters of a prototype filter in paraunitary (PU) CMFB's, we derive a regularity condition for perfect reconstruction (PR) CMFB's. Finally, we design regular 8-channel 32-length PUCMFB and PRCMFB by a unconstrained optimization of residual lattice parameters, and several simulation results for test images are shown for evaluating the proposed image coder based on the CMFB's with one degree of regularity.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"22 6S 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133132596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488801
J. Smith, T. Xia
We present a new method of performing high-resolution path delay testing on designs targeted to Xilinx Virtex-4 field-programmable gate arrays (FPGAs). Our built-in self-test architecture uses an on-chip delay line to set the launch time of test pattern generators to their optimum point for stressing paths in the chip. Consequently, it catches delay defects as small as 78 ps and tests multiple paths in parallel. Our approach was validated on Virtex-4 devices and the same method can be applied to other FPGAs that contain delay lines.
{"title":"High-precision delay testing of Virtex-4 FPGA designs","authors":"J. Smith, T. Xia","doi":"10.1109/MWSCAS.2007.4488801","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488801","url":null,"abstract":"We present a new method of performing high-resolution path delay testing on designs targeted to Xilinx Virtex-4 field-programmable gate arrays (FPGAs). Our built-in self-test architecture uses an on-chip delay line to set the launch time of test pattern generators to their optimum point for stressing paths in the chip. Consequently, it catches delay defects as small as 78 ps and tests multiple paths in parallel. Our approach was validated on Virtex-4 devices and the same method can be applied to other FPGAs that contain delay lines.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115323990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488716
N. Trung, Kwansu Shon, Soo-Won Kim
A highly linear thermal sensitivity delay line for smart temperature sensor is presented. The proposed delay line is a current starved inverter chain. A simple bias current source circuit is incorporated with the delay line to generate a current inversely proportional to temperature based on the transconductance characteristics of a MOS device at the vicinity of the zero temperature coefficient (ZTC) point. Simulation results in a 0.18 mum CMOS technology show that the proposed delay line has a higher linearity within 0.24degC in a wider temperature range from -40degC to 120degC compared with conventional structures.
提出了一种用于智能温度传感器的高线性热敏延迟线。所提出的延迟线是一个电流匮乏的逆变器链。利用MOS器件在零温度系数(ZTC)点附近的跨导特性，将一个简单的偏置电流源电路与延迟线结合，产生与温度成反比的电流。在0.18 μ m CMOS技术上的仿真结果表明，与传统结构相比，该延迟线在-40 ~ 120℃的温度范围内具有更高的0.24℃线性度。
{"title":"A delay line with highly linear thermal sensitivity for smart temperature sensor","authors":"N. Trung, Kwansu Shon, Soo-Won Kim","doi":"10.1109/MWSCAS.2007.4488716","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488716","url":null,"abstract":"A highly linear thermal sensitivity delay line for smart temperature sensor is presented. The proposed delay line is a current starved inverter chain. A simple bias current source circuit is incorporated with the delay line to generate a current inversely proportional to temperature based on the transconductance characteristics of a MOS device at the vicinity of the zero temperature coefficient (ZTC) point. Simulation results in a 0.18 mum CMOS technology show that the proposed delay line has a higher linearity within 0.24degC in a wider temperature range from -40degC to 120degC compared with conventional structures.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124415461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488682
Hua Tang, Matthew Webb
This paper presents a method for optimal synthesis of Delta-Sigma (DeltaSigma) modulator topologies in terms of statistical SNR (Signal-to-Noise Ratio) variation. A DeltaSigma modulator template topology is used to represent many possible Delta-Sigma modulator topologies. Then a symbolic formulation of statistical SNR variation is systematically derived from the template topology so that variation of capacitors are directly translated to SNR variation. To facilitate the search for an optimal topology, a MINLP (Mixed-Integer Nonlinearly Constrained Programming) program is formulated. By solving the MINLP program, an optimal solution with least statistical SNR variation can be obtained. Experiments have shown the solved optimal topologies have less SNR variation compared to traditional ones.
{"title":"Optimal synthesis of Delta-Sigma modulator topologies considering snr variation","authors":"Hua Tang, Matthew Webb","doi":"10.1109/MWSCAS.2007.4488682","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488682","url":null,"abstract":"This paper presents a method for optimal synthesis of Delta-Sigma (DeltaSigma) modulator topologies in terms of statistical SNR (Signal-to-Noise Ratio) variation. A DeltaSigma modulator template topology is used to represent many possible Delta-Sigma modulator topologies. Then a symbolic formulation of statistical SNR variation is systematically derived from the template topology so that variation of capacitors are directly translated to SNR variation. To facilitate the search for an optimal topology, a MINLP (Mixed-Integer Nonlinearly Constrained Programming) program is formulated. By solving the MINLP program, an optimal solution with least statistical SNR variation can be obtained. Experiments have shown the solved optimal topologies have less SNR variation compared to traditional ones.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124803303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488764
A. Elshurafa, E. El-Masry
This paper presents some important design considerations usually ignored that need to be taken into account when designing MEMS parallel plate variable capacitors. Explicitly, it introduces an accurate method that incorporates parasitic and fringing capacitances in calculating the tuning range. Secondly, it shows, by the finite element method, that the etching hole effects for two-plate and three- plate varactors on the capacitance are low and can be ignored in the initial design stages. Finally a novel closed form expression, which calculates the capacitance of a varactor with a warped top suspended plate due to residual stress, is introduced; the expression is based on a second order model.
{"title":"Design considerations in MEMS parallel plate variable capacitors","authors":"A. Elshurafa, E. El-Masry","doi":"10.1109/MWSCAS.2007.4488764","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488764","url":null,"abstract":"This paper presents some important design considerations usually ignored that need to be taken into account when designing MEMS parallel plate variable capacitors. Explicitly, it introduces an accurate method that incorporates parasitic and fringing capacitances in calculating the tuning range. Secondly, it shows, by the finite element method, that the etching hole effects for two-plate and three- plate varactors on the capacitance are low and can be ignored in the initial design stages. Finally a novel closed form expression, which calculates the capacitance of a varactor with a warped top suspended plate due to residual stress, is introduced; the expression is based on a second order model.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124846784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488774
Q. Ho, D. Massicotte
A detector for multirate WCDMA systems based on an adaptive signature method was designed and implemented. Based on an adaptive algorithm, we considered two multirate schemes - the low rate detector and the high rate detector - for variable spreading factor systems. Numerical simulations compared the both multirate schemes in WCDMA scenarios. Hardware complexity of these two multirate schemes was analyzed. Hardware implementation was targeted on Virtex II Pro technology to maximize the number of simultaneous users on one FPGA component.
设计并实现了一种基于自适应签名方法的多速率WCDMA信号检测器。基于自适应算法，我们考虑了两种多速率方案——低速率检测器和高速率检测器——用于可变扩频因子系统。数值模拟比较了两种多速率方案在WCDMA场景下的性能。分析了这两种多速率方案的硬件复杂度。硬件实现以Virtex II Pro技术为目标，以最大限度地增加一个FPGA组件上的同时用户数量。
{"title":"Design and implementation of an adaptive multiuser detector for multirate WCDMA systems","authors":"Q. Ho, D. Massicotte","doi":"10.1109/MWSCAS.2007.4488774","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488774","url":null,"abstract":"A detector for multirate WCDMA systems based on an adaptive signature method was designed and implemented. Based on an adaptive algorithm, we considered two multirate schemes - the low rate detector and the high rate detector - for variable spreading factor systems. Numerical simulations compared the both multirate schemes in WCDMA scenarios. Hardware complexity of these two multirate schemes was analyzed. Hardware implementation was targeted on Virtex II Pro technology to maximize the number of simultaneous users on one FPGA component.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125892167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488691
Jun Zhao, Yong-Bin Kim
A simple neuron model, the FitzHugh-Nagumo (FHN) model, is implemented on field programmable analog arrays (FPAAs). The differential equations of the model is integrated by making arithmetic operations on the reconfigurable voltage model circuits of the FPAAs. The simulation and implementation results demonstrate that FPAA is the viable candidate for the neuron hardware implementation in real time or many orders of magnitude faster.
{"title":"Circuit implementation of FitzHugh-Nagumo neuron model using Field Programmable Analog Arrays","authors":"Jun Zhao, Yong-Bin Kim","doi":"10.1109/MWSCAS.2007.4488691","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488691","url":null,"abstract":"A simple neuron model, the FitzHugh-Nagumo (FHN) model, is implemented on field programmable analog arrays (FPAAs). The differential equations of the model is integrated by making arithmetic operations on the reconfigurable voltage model circuits of the FPAAs. The simulation and implementation results demonstrate that FPAA is the viable candidate for the neuron hardware implementation in real time or many orders of magnitude faster.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126175307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488599
T. Ragheb, S. Kirolos, J. Laska, A. Gilbert, M. Strauss, Richard Baraniuk, Y. Massoud
We develop a framework for analog-to-information conversion based on the theory of information recovery from random samples. The framework enables sub-Nyquist acquisition and processing of wideband signals that are sparse in a local Fourier representation. We present the random sampling theory associated with an efficient information recovery algorithm to compute the spectrogram of the signal. Additionally, we develop a hardware design for the random sampling system that demonstrates a consistent reconstruction fidelity in the presence of sampling jitter, which forms the main source of non-ideality in a practical system implementation.
{"title":"Implementation models for analog-to-information conversion via random sampling","authors":"T. Ragheb, S. Kirolos, J. Laska, A. Gilbert, M. Strauss, Richard Baraniuk, Y. Massoud","doi":"10.1109/MWSCAS.2007.4488599","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488599","url":null,"abstract":"We develop a framework for analog-to-information conversion based on the theory of information recovery from random samples. The framework enables sub-Nyquist acquisition and processing of wideband signals that are sparse in a local Fourier representation. We present the random sampling theory associated with an efficient information recovery algorithm to compute the spectrogram of the signal. Additionally, we develop a hardware design for the random sampling system that demonstrates a consistent reconstruction fidelity in the presence of sampling jitter, which forms the main source of non-ideality in a practical system implementation.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125593753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488548
S. Fattah, W. Zhu, M. Ahmad
In this paper, a new technique for the estimation of the formant frequency of noise-corrupted speech signals is presented. A ramp-cepstrum model for a one-sided autocorrelation function of the voiced speech is proposed considering the vocal-tract system as an autoregressive model with a periodic impulse-train excitation. A residue-based least- squares optimization algorithm is introduced to estimate the ramp-cepstrum model parameters which are then used to compute the formant frequencies. Synthetic and natural vowels as well as some naturally spoken sentences in noisy environments are tested. The experimental results demonstrate the efficacy of the proposed method at low levels of signal-to- noise ratio (SNR).
{"title":"A formant frequency estimation algorithm for speech signals with low signal-to-noise ratio","authors":"S. Fattah, W. Zhu, M. Ahmad","doi":"10.1109/MWSCAS.2007.4488548","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488548","url":null,"abstract":"In this paper, a new technique for the estimation of the formant frequency of noise-corrupted speech signals is presented. A ramp-cepstrum model for a one-sided autocorrelation function of the voiced speech is proposed considering the vocal-tract system as an autoregressive model with a periodic impulse-train excitation. A residue-based least- squares optimization algorithm is introduced to estimate the ramp-cepstrum model parameters which are then used to compute the formant frequencies. Synthetic and natural vowels as well as some naturally spoken sentences in noisy environments are tested. The experimental results demonstrate the efficacy of the proposed method at low levels of signal-to- noise ratio (SNR).","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116001731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488782
Y. Hashizume, Y. Takashima, Y. Nakamura
Since the process technology of LSI devices are developing, the process variation becomes a more critical issue. Especially, the clock skew, which is produced by fabrication variation, causes the serious defects for fabricated chip functions. To improve this problem, the several deskew methods using programmable delay elements (PDEs) have been proposed. However, they need much test cost and PDE cost for an industrial application. We propose a novel method with less PDEs and less test cost by linear programming (LP). The proposed method calculates the each PDE delay using the feasibility check of LP. Our experiment shows that the nondefective chip rate after applying deskew increase 91.6% with 4 PDEs while the nondefective chip rate before applying deskew are 21.2%. The experimental result confirms that our proposed method is effective for improving the yields and relaxing the design margin.
{"title":"A novel clock deskew method by linear programming","authors":"Y. Hashizume, Y. Takashima, Y. Nakamura","doi":"10.1109/MWSCAS.2007.4488782","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488782","url":null,"abstract":"Since the process technology of LSI devices are developing, the process variation becomes a more critical issue. Especially, the clock skew, which is produced by fabrication variation, causes the serious defects for fabricated chip functions. To improve this problem, the several deskew methods using programmable delay elements (PDEs) have been proposed. However, they need much test cost and PDE cost for an industrial application. We propose a novel method with less PDEs and less test cost by linear programming (LP). The proposed method calculates the each PDE delay using the feasibility check of LP. Our experiment shows that the nondefective chip rate after applying deskew increase 91.6% with 4 PDEs while the nondefective chip rate before applying deskew are 21.2%. The experimental result confirms that our proposed method is effective for improving the yields and relaxing the design margin.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122635561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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