Strained Si NMOSFETs for high performance CMOS technology

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI:10.1109/VLSIT.2001.934946

K. Rim, S. J. Koester, Michael J. Hargrove, J. Chu, Patricia M. Mooney, John A. Ott, T. Kanarsky, P. Ronsheim, M. Ieong, A. Grill, Hon-Sum Philip Wong

引用次数: 139

Abstract

Performance enhancements in strained Si NMOSFETs were demonstrated at L/sub eff/<70 nm. A 70% increase in electron mobility was observed at vertical fields as high as 1.5 MV/cm for the first time, suggesting a new mobility enhancement mechanism in addition to reduced phonon scattering. Current drive increase by /spl ges/35% was observed at L/sub eff/<70 nm. These results indicate that strain can be used to improve CMOS device performance at sub-100 nm technology nodes.

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用于高性能CMOS技术的应变Si nmosfet

应变Si nmosfet的性能在L/sub /<70 nm处得到了增强。在高达1.5 MV/cm的垂直场下，首次观察到电子迁移率提高了70%，这表明除了减少声子散射外，还有一种新的迁移率增强机制。在L/sub /<70 nm处，电流驱动增大了35%。这些结果表明，应变可以用来提高CMOS器件在亚100纳米技术节点上的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

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