Test Frequency Compaction for Fault Detection in Analog Circuits Using Sensitivity Analysis

Abstract

In this paper, we present a methodology to test faults induced by large deviations in components in analog circuits through multi-frequency test based on sensitivity analysis. Final compaction of the test frequencies is done using a covering table optimization method. Test Frequency compaction and choice of observation points are based on a novel notation of fault equivalence and sensitivity curves. Our case study shows this method can effectively minimize the sinusoid test frequencies to separate the fault-free and faulty operations of the circuit under test for all faulty components.