TORSIM: An efficient fault simulator for synchronous sequential circuits

Abstract

The paper describes a new approach to the fault simulation of synchronous sequential circuits. Its novelty comes from combining the event-driven compiled-code simulation technique proposed by H. K. Lee and D. S. Ha (1992) with the single fault propagation fault-parallel fault simulation algorithm used by F. Maamari and J. Rajski (1988). Our approach is particularly suited for those applications requiring the fault simulation of very high numbers of input patterns, like signature computation or fault dictionary construction. A fault simulator named TORSIM has been written to verify the effectiveness of the approach. The results we present show an average speed-up in terms of CPU time of more than one order of magnitude with respect to the ones reported by Maamari and Rajski.<>