Testing and Modeling of Board Level Reliability of WLCSP under UHAST Conditions

Abstract

Board-level reliability of wafer level chip scale package (WLCSP) is studied by both experiments and numerical modeling in this paper. The test condition is unbiased highly accelerated stress test (UHAST) followed by electrical inspections. One sample failed the test, and failure analysis showed that the failed sample has solder joint degradation and back metal peeling issues. To understand the failure mechanism, nonlinear hygro-thermal-mechanical modeling was performed. To simulate the moisture-induced stresses, the equivalent diffusion expansion coefficient (CDE) method is adopted. Simplification are made for UHAST condition with uniform moisture distribution but without the vapor pressure effects at equilibrium. A total of 7 numerical cases were studied and compared. The simulation results showed that the solder joint plastic strains increases significantly after mounting to the PCB and applying the UHAST conditions. This is mainly due to the CTE and CDE mismatch between the PCB and the device. On the other hand, the peeling stresses at the die and back metal decrease after PCB mounting under UHAST compared to device-only scenario. It is assumed that there is loss of adhesion between the die and the back metal under extreme moisture conditions. Finally, the simulation confirmed that reducing back coating thickness can effectively reduce both the solder joint plastic strains and metal-silicon interfacial stresses, thus providing a feasible solution to enhance the reliability of the package.