{"title":"Channel material optimization for the ultimate planar and nanowire mosfets: a theoretical exploration","authors":"Jing Wang, M. Lundstrom","doi":"10.1109/DRC.2005.1553139","DOIUrl":null,"url":null,"abstract":"Modem MOSFETs have channel lengths below 50 nm, and billion transistor logic chips have arrived. Moore's Law continues, but the end of MOSFET scaling is in sight. Many researchers are exploring new materials and device structures to push MOS technology towards fundamental limits. MOSFETs with strained silicon, SiGe, or even III-V channels are possibilities, as are one-dimensional channels made from nanowires or nanotubes. In this paper, we theoretically examine the impact of the channel material property (i.e., E(k)) and device structure (i.e., 2D planar vs. ID nanowire) on the ultimate performance of ballistic MOSFETs. The objective is to identify an optimum channel material for the ultimate planar/nanowire MOSFETs. The results show that when the transport effective mass is small, it degrades device performance, and that planar and nanowire MOSFETs behave differently. Different channel materials display different E(k) relations and different effective mass at the band-edge. To achieve high device performance, one might expect that a light transport effective mass would be best since it offers a high carrier injection velocity. On the other hand, a light effective mass also leads to a lower quantum (or semiconductor) capacitance, which degrades the ON-current of the device. When the channel length is sufficiently small, strong source-to-drain (S/D) tunneling occurs at a small transport effective mass. Tunneling degrades the subthreshold characteristics of the FET and consequently lowers the ON-current for the same OFF-current. For these reasons, an optimum transport effective mass may exist for a given device structure.","PeriodicalId":306160,"journal":{"name":"63rd Device Research Conference Digest, 2005. DRC '05.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"63rd Device Research Conference Digest, 2005. DRC '05.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2005.1553139","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Modem MOSFETs have channel lengths below 50 nm, and billion transistor logic chips have arrived. Moore's Law continues, but the end of MOSFET scaling is in sight. Many researchers are exploring new materials and device structures to push MOS technology towards fundamental limits. MOSFETs with strained silicon, SiGe, or even III-V channels are possibilities, as are one-dimensional channels made from nanowires or nanotubes. In this paper, we theoretically examine the impact of the channel material property (i.e., E(k)) and device structure (i.e., 2D planar vs. ID nanowire) on the ultimate performance of ballistic MOSFETs. The objective is to identify an optimum channel material for the ultimate planar/nanowire MOSFETs. The results show that when the transport effective mass is small, it degrades device performance, and that planar and nanowire MOSFETs behave differently. Different channel materials display different E(k) relations and different effective mass at the band-edge. To achieve high device performance, one might expect that a light transport effective mass would be best since it offers a high carrier injection velocity. On the other hand, a light effective mass also leads to a lower quantum (or semiconductor) capacitance, which degrades the ON-current of the device. When the channel length is sufficiently small, strong source-to-drain (S/D) tunneling occurs at a small transport effective mass. Tunneling degrades the subthreshold characteristics of the FET and consequently lowers the ON-current for the same OFF-current. For these reasons, an optimum transport effective mass may exist for a given device structure.