Reducing soft-error vulnerability of caches using data compression

Abstract

With ongoing chip miniaturization and voltage scaling, particle strike-induced soft errors present increasingly severe threat to the reliability of on-chip caches. In this paper, we present a technique to reduce the vulnerability of caches to soft-errors. Our technique uses data compression to reduce the number of vulnerable data bits in the cache and performs selective duplication of more critical data-bits to provide extra protection to them. Microarchitectural simulations have shown that our technique is effective in reducing cache vulnerability and outperforms another technique. For single and dual-core system configuration, the average reduction in cache vulnerability is 5.59× and 8.44×, respectively. Also, the implementation and performance overheads of our technique are minimal and it is useful for a broad range of workloads.