R. Choi, Hyun‐Yong Yu, Hyungsub Kim, H. Ryu, H. Bae, K. K. Choi, Yong-Won Cha, C. Choi
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引用次数: 3
Abstract
We have studied low temperature processes for monolithic 3D integration platform development including hydrogen/helium ion implantation-based wafer cleavage & bonding (<; 450°C), low temperature (<; 550°C) in-situ doped S/D selective SiGe epi process, low temperature (<; 200°C) gate stack on the chemical-mechanical polished (CMP) wafer, and green-lased annealing. These unit technologies can be adopted to achieve 3D integration platform technology for the high performance and low power applications.
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