A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs

Abstract

A framework for integrating boundary scan (IEEE 1149.1) with board-level self-testing of word-oriented, multiport static RAM chips is proposed. Innovative parallel versions of functional duplex march tests (FDMs) for detecting complex couplings are developed. This approach produces significantly smaller cycle-time penalty during normal operation than built-in self-testing (BIST). It produces two orders of magnitude test acceleration as compared to pure boundary scan testing without BIST (i.e., by using EXTEST and SAMPLE/PRELOAD instructions only).