{"title":"Yield and cost estimation for a CAM based parallel processor","authors":"W. B. Noghani, I. Jalowiecki","doi":"10.1109/MTDT.1995.518091","DOIUrl":null,"url":null,"abstract":"A comprehensive model is developed to estimate yield values for an associative string processor (ASP) chip which is populated with content addressable memory (CAM). The yield model comprises analysis of row and column redundancy strategies for the CAM combined with floor planning of the processor architecture. At the end, a cost model is developed, based on some actual fabrication costs, in order to optimise the processor according to a suitable figure of merit.","PeriodicalId":318070,"journal":{"name":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.1995.518091","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A comprehensive model is developed to estimate yield values for an associative string processor (ASP) chip which is populated with content addressable memory (CAM). The yield model comprises analysis of row and column redundancy strategies for the CAM combined with floor planning of the processor architecture. At the end, a cost model is developed, based on some actual fabrication costs, in order to optimise the processor according to a suitable figure of merit.
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