J. Compiet, P. D. Jong, P. Wambacq, G. Vandersteen, S. Donnay, D. M. Engels, I. Bolsens
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引用次数: 7
Abstract
A hierarchical high-level model of a high-speed flash ADC is presented. The input parameter list is extracted from a 400 MHz, 4-bit, flash ADC designed in HSPICE in a 0.35 /spl mu/m CMOS technology. A speedup in simulation time of 5000 is reported compared to the 3-bit flash ADC HSPICE simulations. The accuracy of the model is verified with HSPICE simulations and shows a good agreement.
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