A placement optimization technique for 3D IC

Abstract

This paper presents a placement algorithm for designing 3D Integrated Circuits (ICs). Typical 2D ICs are unable to provide the high connection speeds that are offered by its 3D variants at a lower cost, consuming less power and space. The algorithm proposed in this paper demonstrates that assigning blocks to each layer in a compact fashion can achieve substantial savings in the total wirelength along with a reduction in the number of TSVs in most of the cases. On the whole, our method helps to reduce the total wirelength, as well as number of TSVs, while satisfying the area-constraints.