Memory package with LOC structure using new adhesive material

H. Nakayoshi, N. Izawa, T. Ishikawa, T. Suzuki
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引用次数: 3

Abstract

The LOC (Lead On Chip) structure has been considered as an effective technology to encapsulate a large LSI memory chip into a small package. The main feature of the structure is contact of leadframes onto the active chip area with adhesive sandwiched in between. Therefore, the design concept of LOC greatly depends on the characteristics of the adhesive layer. The key technologies for LOC development are summarized as: 1. To lessen damage on chip during die-attach and wire bonding; 2. To secure sufficient wire bendability above the organic adhesive; and 3. To reduce package crack rate during the solder reflowing process. We have developed a new adhesive tape which is composed of single-layer thermoplastic polyimide siloxanes. Due to the absence of a base film, the single layer adhesive can be fabricated to any desirable thickness. During its softening process, the thick adhesive film encloses dust that, otherwise, could damage the chip surface. These properties, by providing a large Young's modulus of the film at high temperature and contamination-free lead surface, enable us to secure sufficient lead-wire bendability. The other materialistic advantage of the adhesive is its low moisture absorption. The low moisture absorption results in high resistance against package crack caused by the solder reflowing process. In this paper, we describe how we have selected the LOC adhesive tape through the evaluations of the assembly process and have successfully developed a highly productive and reliable memory package with LOC structure.<>
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采用新型粘接材料的LOC结构内存封装
导联芯片(Lead On Chip)结构被认为是将大型LSI存储芯片封装在小封装中的有效技术。该结构的主要特点是引线框与主动芯片区域接触,中间夹有粘合剂。因此,LOC的设计理念在很大程度上取决于粘接层的特性。LOC开发的关键技术总结为:1。减少贴模和焊线过程中对芯片的损坏;2. 确保金属丝在有机粘合剂上有足够的可弯曲性;和3。降低焊料回流过程中封装的裂纹率。我们研制了一种由单层热塑性聚酰亚胺硅氧烷组成的新型胶带。由于没有基膜,单层粘合剂可以制造成任何所需的厚度。在其软化过程中,厚厚的胶膜包围灰尘,否则可能会损坏芯片表面。这些特性,通过在高温下提供大的杨氏模量的薄膜和无污染的铅表面,使我们能够确保足够的引线可弯曲性。胶粘剂的另一个材料优势是它的低吸湿性。低吸湿性使其具有很高的抗焊料回流过程引起的封装裂纹的能力。在本文中,我们描述了我们如何通过对装配过程的评估来选择LOC胶带,并成功开发出具有LOC结构的高生产率和可靠的存储封装
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Development of a tapeless lead-on-chip (LOC) package A photosensitive-BCB on laminate technology (MCM-LD) A PC program that generates a model of the parasitics for IC packages Compact planar optical devices (CPODs) by CVD technology Predicting solder joint shape by computer modeling
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