Pub Date : 1994-11-25DOI: 10.1109/ECTC.1994.367546
M. Amagai, R. Baumann, S. Kamei, M. Ohsumi, E. Kawasaki, H. Kitagawa
A double-sided adhesive tape is typically used as an insulator and mechanical buffer layer between the chip and lead frame in lead-on-chip (LOC) packages. The costs associated with the lead frame and tape process make the current LOC package ten times more expensive than conventional packaging. A new tapeless LOC package process has been developed which significantly reduces the production costs. In this new process, the tape is replaced by a thermoplastic adhesive layer deposited on the polyimide coated wafer. This paper describes the optimum thermoplastic material properties for the adhesive layer, the fabrication process parameters, and the experimental and simulated reliability and performance results of the tapeless LOC package.<>
{"title":"Development of a tapeless lead-on-chip (LOC) package","authors":"M. Amagai, R. Baumann, S. Kamei, M. Ohsumi, E. Kawasaki, H. Kitagawa","doi":"10.1109/ECTC.1994.367546","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367546","url":null,"abstract":"A double-sided adhesive tape is typically used as an insulator and mechanical buffer layer between the chip and lead frame in lead-on-chip (LOC) packages. The costs associated with the lead frame and tape process make the current LOC package ten times more expensive than conventional packaging. A new tapeless LOC package process has been developed which significantly reduces the production costs. In this new process, the tape is replaced by a thermoplastic adhesive layer deposited on the polyimide coated wafer. This paper describes the optimum thermoplastic material properties for the adhesive layer, the fabrication process parameters, and the experimental and simulated reliability and performance results of the tapeless LOC package.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124692837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367619
A. Singer
In the development of a given technology, the process costs must be understood if commercial scale production is to be successful. To achieve this goal, Technical Cost Modeling has evolved from traditional costing methodologies in order to estimate the dynamics of a system of manufacture, and to be used as a tool for determining optimal scale-up conditions. For the manufacture of thermal management chemical vapor deposition (CVD) diamond, cost models have been developed in older to estimate the appropriate scale-up conditions for different CVD diamond deposition and finishing technologies in order to fabricate diamond substrates for electronics packaging. Subsequent cost analysis is then undertaken to assess the viability of diamond as an electronics packaging material. With this ability to identify the cost of future manufacturing scenarios, the R&D pace of a promising technology can be quickened, or the investment schedule in an unfavorable technology can be phased out.<>
{"title":"Polycrystalline CVD diamond in electronics: important cost factors","authors":"A. Singer","doi":"10.1109/ECTC.1994.367619","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367619","url":null,"abstract":"In the development of a given technology, the process costs must be understood if commercial scale production is to be successful. To achieve this goal, Technical Cost Modeling has evolved from traditional costing methodologies in order to estimate the dynamics of a system of manufacture, and to be used as a tool for determining optimal scale-up conditions. For the manufacture of thermal management chemical vapor deposition (CVD) diamond, cost models have been developed in older to estimate the appropriate scale-up conditions for different CVD diamond deposition and finishing technologies in order to fabricate diamond substrates for electronics packaging. Subsequent cost analysis is then undertaken to assess the viability of diamond as an electronics packaging material. With this ability to identify the cost of future manufacturing scenarios, the R&D pace of a promising technology can be quickened, or the investment schedule in an unfavorable technology can be phased out.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115384316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367564
J. Davis, J. K. Arledge
Metallization of three-dimensional (3D) molded polymer substrates by sputtering technology is an exciting alternative to traditional electroless plating processes. The technology offers the ability to rapidly coat the 3D circuit base without the use of precious metal catalysts or plating baths that may be environmentally harmful. Consequently, sputter coating of 3D circuits offers the advantages of high through-put and flexible manufacturing while minimizing disposable wastes. This paper focuses on the critical issues affecting the performance of sputtered thin film on 3D polymer substrates.<>
{"title":"Thin film metallization of three-dimensional substrates","authors":"J. Davis, J. K. Arledge","doi":"10.1109/ECTC.1994.367564","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367564","url":null,"abstract":"Metallization of three-dimensional (3D) molded polymer substrates by sputtering technology is an exciting alternative to traditional electroless plating processes. The technology offers the ability to rapidly coat the 3D circuit base without the use of precious metal catalysts or plating baths that may be environmentally harmful. Consequently, sputter coating of 3D circuits offers the advantages of high through-put and flexible manufacturing while minimizing disposable wastes. This paper focuses on the critical issues affecting the performance of sputtered thin film on 3D polymer substrates.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"4 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116663432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367494
Seung-Ho Ahn, Young-shin Kwon, Kwangbok Shin
For the purpose of studying popcorn phenomena, plastic ball grid array packages with 119 I/O's were tested under the pre-conditioning test conditions. Observations using scanning acoustic tomography and optical microscopy were carried out to investigate the existence of delaminations and cracks in the package, and the cracking patterns after IR reflow. Package deformations and thermo-mechanical stress distributions in the package were calculated by the finite element method. Three types of substrates were tried to prove that open thermal viaholes under die pad could prevent popcorn cracking during IR reflow. From the experiments and the observations, it was concluded that package cracking, which was caused by the expansion of moisture concentrated at the die adhesive layer, could be prevented using open thermal viaholes under die pad. The open thermal viaholes acted as vent holes, through which the expanded water vapor could go outside, not causing popcorn cracking. The die-attach process using U.V. tape was effective in the assembly of the packages with open thermal viaholes.<>
{"title":"Popcorn phenomena in a ball grid array package","authors":"Seung-Ho Ahn, Young-shin Kwon, Kwangbok Shin","doi":"10.1109/ECTC.1994.367494","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367494","url":null,"abstract":"For the purpose of studying popcorn phenomena, plastic ball grid array packages with 119 I/O's were tested under the pre-conditioning test conditions. Observations using scanning acoustic tomography and optical microscopy were carried out to investigate the existence of delaminations and cracks in the package, and the cracking patterns after IR reflow. Package deformations and thermo-mechanical stress distributions in the package were calculated by the finite element method. Three types of substrates were tried to prove that open thermal viaholes under die pad could prevent popcorn cracking during IR reflow. From the experiments and the observations, it was concluded that package cracking, which was caused by the expansion of moisture concentrated at the die adhesive layer, could be prevented using open thermal viaholes under die pad. The open thermal viaholes acted as vent holes, through which the expanded water vapor could go outside, not causing popcorn cracking. The die-attach process using U.V. tape was effective in the assembly of the packages with open thermal viaholes.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"261 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121214013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367549
H. Longworth, E. Perfecto, P. Mclaughlin
IBM Microelectronics has evaluated the reliability of structures built by various processes which we developed for multilevel thin film (MLTF) applications. Two distinct processes were used for the building of conformal copper-polyimide structures on alumina ceramic: Laser ablation of the polyimide for via patterning and wiring defined by subtractive etching of Cr/Cu/Cr, and photosensitive polyimide for via patterning and wiring defined by electroplating through a resist. Reliability evaluation was performed on test-vehicles with both MLTF processes by a combination of IBM standard and MIL-STD-883 stress procedures. These stresses were designed to monitor any potential reliability problems due to metal migration, corrosion (or contamination), metal fatigue, and poor step coverage. Electrical measurements were done before, during, and after stress to check for opens and inter and intralevel shorts. At completion of stressing, no failures were observed in either type of test vehicles. This indicates that both processes meet or exceed IBM current product reliability standards.<>
{"title":"Reliability evaluation of multilevel thin film structures","authors":"H. Longworth, E. Perfecto, P. Mclaughlin","doi":"10.1109/ECTC.1994.367549","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367549","url":null,"abstract":"IBM Microelectronics has evaluated the reliability of structures built by various processes which we developed for multilevel thin film (MLTF) applications. Two distinct processes were used for the building of conformal copper-polyimide structures on alumina ceramic: Laser ablation of the polyimide for via patterning and wiring defined by subtractive etching of Cr/Cu/Cr, and photosensitive polyimide for via patterning and wiring defined by electroplating through a resist. Reliability evaluation was performed on test-vehicles with both MLTF processes by a combination of IBM standard and MIL-STD-883 stress procedures. These stresses were designed to monitor any potential reliability problems due to metal migration, corrosion (or contamination), metal fatigue, and poor step coverage. Electrical measurements were done before, during, and after stress to check for opens and inter and intralevel shorts. At completion of stressing, no failures were observed in either type of test vehicles. This indicates that both processes meet or exceed IBM current product reliability standards.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"28 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125861923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367556
H. Rosten, R. Viswanath
Large mono-chip packages show a trend of increasing power dissipation and power density: for example the maximum dissipation of the Pentium processor is 16 Watts compared to the 6 Watts of its 80486 predecessor. This poses challenges for equipment designers to provide satisfactory thermal environments for reliable package operation. This paper provides an example of a component manufacturer and a thermal-analysis software vendor working together to construct and validate a thermal model of first-level packaging of a die (the Pentium processor) that can be used by equipment designers concerned with second- and third-level packaging. It is proposed that this example might set a pattern for the future.<>
{"title":"Thermal modelling of the Pentium processor package","authors":"H. Rosten, R. Viswanath","doi":"10.1109/ECTC.1994.367556","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367556","url":null,"abstract":"Large mono-chip packages show a trend of increasing power dissipation and power density: for example the maximum dissipation of the Pentium processor is 16 Watts compared to the 6 Watts of its 80486 predecessor. This poses challenges for equipment designers to provide satisfactory thermal environments for reliable package operation. This paper provides an example of a component manufacturer and a thermal-analysis software vendor working together to construct and validate a thermal model of first-level packaging of a die (the Pentium processor) that can be used by equipment designers concerned with second- and third-level packaging. It is proposed that this example might set a pattern for the future.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125547568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367591
J. Day, S. Gupta
Improved technologies have been developed to manufacture 0.1 /spl mu/F surface mountable ceramic chips in the 0603 size. A new dielectric based on barium titanate was developed with a Y5V temperature characteristic to achieve maximum dielectric constant. These parts achieve excellent electrical and mechanical reliability and are robust in wave soldering processes. To minimize cost the dielectric was designed to fire at 1145/spl deg/C by adding compatible low melting glass frit in order to use low cost electrodes with a high percentage of silver. In order to increase the capacitance per layer improved manufacturing processes were developed to achieve thin dielectric layers and narrow electrode side margins.<>
{"title":"A new Y5V 0603 0.1 /spl mu/F ceramic chip capacitor","authors":"J. Day, S. Gupta","doi":"10.1109/ECTC.1994.367591","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367591","url":null,"abstract":"Improved technologies have been developed to manufacture 0.1 /spl mu/F surface mountable ceramic chips in the 0603 size. A new dielectric based on barium titanate was developed with a Y5V temperature characteristic to achieve maximum dielectric constant. These parts achieve excellent electrical and mechanical reliability and are robust in wave soldering processes. To minimize cost the dielectric was designed to fire at 1145/spl deg/C by adding compatible low melting glass frit in order to use low cost electrodes with a high percentage of silver. In order to increase the capacitance per layer improved manufacturing processes were developed to achieve thin dielectric layers and narrow electrode side margins.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130585131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367597
M. Caggiano, C. De Angelis
The Package Parasitic Model Program is a PC program, that can generate a model of package parasitics for either dual-in-line or for quad flat pack IC packages. The user enters simple dimensional information for the geometries of the package from the package drawings. This information is easy to obtain and some of the more common dimensions can be defaulted if their values are unknown. The program, written in C, then constructs the proposed package layout and calculates each lead's self inductance; its mutual inductance, mutual capacitance and the capacitance to a ground plane if one exists. The whole process of data entry and computer simulation usually takes just a few minutes on a 386 based PC. Results of benchmark package simulations agree to within 10% of hand calculations employing the reference's equations and drawings of the package. The Package Parasitic Model Program is helpful in integrated circuit package design and analysis. It saves the time of tedious data entry required in the more sophisticated three dimensional programs that use large amounts of CPU time on work stations.<>
{"title":"A PC program that generates a model of the parasitics for IC packages","authors":"M. Caggiano, C. De Angelis","doi":"10.1109/ECTC.1994.367597","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367597","url":null,"abstract":"The Package Parasitic Model Program is a PC program, that can generate a model of package parasitics for either dual-in-line or for quad flat pack IC packages. The user enters simple dimensional information for the geometries of the package from the package drawings. This information is easy to obtain and some of the more common dimensions can be defaulted if their values are unknown. The program, written in C, then constructs the proposed package layout and calculates each lead's self inductance; its mutual inductance, mutual capacitance and the capacitance to a ground plane if one exists. The whole process of data entry and computer simulation usually takes just a few minutes on a 386 based PC. Results of benchmark package simulations agree to within 10% of hand calculations employing the reference's equations and drawings of the package. The Package Parasitic Model Program is helpful in integrated circuit package design and analysis. It saves the time of tedious data entry required in the more sophisticated three dimensional programs that use large amounts of CPU time on work stations.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114208205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367497
P. Martino, G. M. Freedman, L. Rácz, J. Szekely
Predictions of surface mount or through hole solder joint shape, based on the lead and pad geometry, solder volume, and material characteristics, can be used to improve soldering yield. This paper reports on a collaboration between Digital Equipment Corporation and Massachusetts Institute of Technology to develop a method to predict solder joint shapes. It concentrates on the application of a public domain software program called Surface Evolver to solder joint modeling. Surface Evolver uses numerical optimization techniques to compute the shape of capillary surfaces. Solder joints are one of many applications of Surface Evolver. It seems to be well suited to compute the shape of complex solder joints. Results from Surface Evolver are compared to shapes computed by other means, and to the shape of actual solder joints. Good agreement is obtained in most cases.<>
{"title":"Predicting solder joint shape by computer modeling","authors":"P. Martino, G. M. Freedman, L. Rácz, J. Szekely","doi":"10.1109/ECTC.1994.367497","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367497","url":null,"abstract":"Predictions of surface mount or through hole solder joint shape, based on the lead and pad geometry, solder volume, and material characteristics, can be used to improve soldering yield. This paper reports on a collaboration between Digital Equipment Corporation and Massachusetts Institute of Technology to develop a method to predict solder joint shapes. It concentrates on the application of a public domain software program called Surface Evolver to solder joint modeling. Surface Evolver uses numerical optimization techniques to compute the shape of capillary surfaces. Solder joints are one of many applications of Surface Evolver. It seems to be well suited to compute the shape of complex solder joints. Results from Surface Evolver are compared to shapes computed by other means, and to the shape of actual solder joints. Good agreement is obtained in most cases.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114538190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-01DOI: 10.1109/ECTC.1994.367643
H.A. Jensen, A.O. Cifuentes
This paper presents a technique to study the sensitivity of the dynamic response of an electronic system as a function of some of its design parameters. In this approach the system parameters are defined in terms of some nominal value plus a deviatoric component. Different sensitivity measures for the electronic component response are characterized in terms of the statistical moments of the response or the coefficient of variation. This method is expected to be useful in the design, analysis and qualification of electronic components.<>
{"title":"Probabilistic sensitivity analysis for the dynamic response of electronic systems: a study of the interactions of molding compound and die attach adhesive, with regards to package cracking","authors":"H.A. Jensen, A.O. Cifuentes","doi":"10.1109/ECTC.1994.367643","DOIUrl":"https://doi.org/10.1109/ECTC.1994.367643","url":null,"abstract":"This paper presents a technique to study the sensitivity of the dynamic response of an electronic system as a function of some of its design parameters. In this approach the system parameters are defined in terms of some nominal value plus a deviatoric component. Different sensitivity measures for the electronic component response are characterized in terms of the statistical moments of the response or the coefficient of variation. This method is expected to be useful in the design, analysis and qualification of electronic components.<<ETX>>","PeriodicalId":344532,"journal":{"name":"1994 Proceedings. 44th Electronic Components and Technology Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114703213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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