Global Optimization of MCMs with ASICs Using Concurrent Engineering

Abstract

This paper describes a large MCM developed for space applications. Design constraints were extremely severe: low volume, low weight, high signal speed, minimum power consumption, high pressure, exposition to space vacuum. The MCM includes 1.2 million of transistors. It required the design of 8 different types of ASICs in 3 different technologies: CMOS, ECL, mixed-signal bipolar. The substrate has been fabricated using Dassault Electronique's high-density photo-imageable thick-film process (PCM technology), that is briefly described in this paper. An Aluminium package was used to save weight and improve thermal conduction. Stand-offs sustaining the lid were used to handle high pressure. The MCM and the ASICs were concurrently designed to simplify the layout of the MCM as much as possible. Despite high routing density, only 4 layers were used. Heavy traffic was "pushed" into ASICs where there is no significant extra cost associated with connections. The ASIC pads were arranged to match MCM wires. A global Design-For-Test strategy has been implemented. The ASICs include internal and external Built-In Self Test (BIST) resources, that allow to test the ASICs and the MCM connections at full speed and with no external test vectors. Test modes can be controlled and defaults can be located through a single test bus based on the IEEE 1149.1 (JTAG) standard. The MCM can be fully tested with no other test equipment than a standard PC connected to its test bus.