Exploring Resource-Aware Deep Neural Network Accelerator and Architecture Design

Abstract

Due to the ever-increasing number of neural networks(NNs) connections and parameters, computation on neural networks is becoming both power hankering and memory intensive. In this paper, we propose a sparse neural networks accelerator to improve memory resource utilization and improve power efficiency. In contrast to prior works, we introduce a highly integrated software and hardware co-design technique that combines resource-aware software compression algorithms and specialized hardware inference engine in the accelerator. Compared with other designs, our design can compress parameters by 90× and substantially improve storage resource utilization, performance (6.9×) and power (1.2×) for NN accelerators.