Concurrent system level test (CSLT) methodology for complex system-on-chip

Abstract

Technological advancements in semi-conductor manufacturing industries have helped packing billions of transistors on a single piece of silicon chip also known as system-on-chip (SoC). The SoCs have evolved to a stage where more discrete functions are being integrated to form a complex SoC chip. With these increasing functionalities, there is a growing need for an additional test platform besides ATE, which can ensure end user experience level testing. System level test (SLT) is one such test platform that ensures end user experience testing (e.g., non-deterministic) by executing multiple test cases on different operating systems under varying test conditions in a sequential manner. With increased functionality, there is a need for additional test coverage at SLT, leading to more test time due to the fact that SLT is being done in a sequential manner, hence impacting the overall test cost. This paper discusses the importance of SLT and introduces the idea of concurrent system level test (CSLT) (i.e., a way to identify mutually exclusive test cases and execute them in parallel). CSLT methodology helps in reducing the test time without compromising on test quality. Experimental results have shown 20 to 25% reduction in test time with this method.