An FPGA-based hardware implementation of visual based fall detection

Abstract

The independent living of the elderly population is very much of a concern and threaten due to their high tendency in falling. As the worldwide aging population grows tremendously, there is a need of reliable fall detection solution which operates in real-time at high accuracy and supports large scale implementation. Highly promising tool like Field Programmable Gate Array (FPGA) had been commonly used as a hardware accelerator in many emerging embedded vision based systems due to its high performance and low power consumption. As a result, it is the main objective of this work to propose a solution of FPGA-based visual based fall detection to meet the stringent real-time requirement. Our solution implemented in low-cost FPGA is able to achieve a performance of 58.36fps at VGA resolutions (640×480) through the exploitation of the parallel and pipeline architecture of FPGA. Besides, the optimization techniques that we proposed are able to reduce up to 33.33% of the dynamic power consumption of the system. The outputs of this work demonstrate the great impacts and potentials of FPGA's flexibility and scalability in the future healthcare industry.