Delay Insensitive logic with increased fault tolerance and optimized for subthreshold operation

Abstract

Biomedical and space applications require both reduced power consumption - extending the life of the battery - as well as reliable operation in harsh conditions particularly in the context of radiation or noise sources. A common approach for reducing power is to lower the supply voltage to the subthreshold regime (Vdd <; Vth). However, subthreshold operation also results in an increased vulnerability to radiation and noise as well as an exponential increase in delay variation of the circuits and associated clock trees, which may lead to incorrect operation. Asynchronous logic has shown a natural adaptation to subthreshold operation due to the replacement of the clock by the efficient implementation of handshaking signals and communication protocols - eliminating the sensitivity to delay variation as well as a further reduction of power by eliminating the highly active clock. Delay Insensitive logic mitigates the performance reduction and delay variation sensitivity of subthreshold circuits but does not address the reduction in fault tolerance. Consequently, a fault tolerant scheme applied to current NULL Convention LogicTM (NCL) gates is proposed - providing tolerance to Single Event Upset (SEU) provoked by radioactivity, while operating in the subthreshold region. Although the values of critical charge (Qcrit) decrease dramatically for traditional NCL cells from 189 fC @ 1.5 V to 26 fC @ 0.3 V, the proposed cells - simulated with MIT Lincoln Lab's 150 nm XLP CMOS process - were virtually fault tolerant (Qcrit > 1000 fC) for both supply voltages.