A linear systolic array for the 2-D discrete cosine transform

Abstract

In this paper, we propose a linear systolic array of N basic cells (including 2N multipliers) for computing the two-dimensional (2-D) N/spl times/N-point discrete cosine transform (DCT). The array is based on the row-column decomposition but involves no matrix transposition problems. The proposed architecture is highly regular, modular, and thus very suitable for VLSI implementation. Also, it has an efficiency of 100 percent and a throughput of one N/spl times/N-point transform per N/sup 2/ cycles. As compared to existing array structures for the 2-D DCT, the proposed one achieves lower or the same area-time complexity with better regularity. Without change in circuit design, it can be directly used to compute the 2-D N/spl times/N-point inverse DCT and other discrete sinusoidal transforms, such as the discrete sine transform and the discrete Hartley transform. By using the GENESIL CAD tool we design a prototype chip of the proposed linear array for the 8/spl times/8-point DCT in a 0.8 /spl mu/m CMOS technology. The chip requires a die size of about 6.95 mm/spl times/6.9 mm (including 108363 transistors) and is able to operate at a clock rate up to 33 MHz.