Power consumption in fast dividers using time shared TMR

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI:10.1109/DFTVS.1999.802892

W. Gallagher, E. Swartzlander

引用次数: 2

Abstract

The Newton-Raphson algorithm and Goldschmidt's algorithm (series expansion) are two popular methods of implementing division. Both are based on multiplication and converge quadratically to the result over several iterations. Applying time shared triple modular redundancy (TSTMR), a fault tolerance technique, to such a divider requires using a smaller multiplier and triplicating the divider circuit. To reduce division latency, the division algorithm can be modified to use lower precision multiplications during early iterations. This work summarizes and compares several important properties of these dividers: latency, area, average power dissipation and energy per divide.

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使用分时TMR的快速分压器的功耗

Newton-Raphson算法和Goldschmidt算法(级数展开)是实现除法的两种常用方法。两者都基于乘法，并在多次迭代后以二次收敛的方式收敛于结果。将时间共享三模冗余(TSTMR)，一种容错技术应用于这样的分频器，需要使用更小的乘法器和三倍分频电路。为了减少除法延迟，可以修改除法算法，以便在早期迭代期间使用更低精度的乘法。这项工作总结并比较了这些分频器的几个重要特性:延迟、面积、平均功耗和每次分频的能量。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)

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