{"title":"A transmitter and receiver interface circuit including an equalizer and PFLL for 150 Mbit/s cable communication","authors":"J. Routama, K. Koli, P. Ruhanen, K. Halonen","doi":"10.1109/CICC.1997.606637","DOIUrl":null,"url":null,"abstract":"This paper describes a single chip transmitter and receiver interface circuit for 150 Mbit/s CMI-coded data transmission. The receiver circuit includes a 12 dB cable equalizer to compensate nonconstant cable attenuations and a PFLL for data regeneration. The transmitter includes a cable driver which supplies a stable IVpp signal amplitude to the transmission line and a PLL to extract a 310 MHz clock signal.","PeriodicalId":111737,"journal":{"name":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of CICC 97 - Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1997.606637","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
This paper describes a single chip transmitter and receiver interface circuit for 150 Mbit/s CMI-coded data transmission. The receiver circuit includes a 12 dB cable equalizer to compensate nonconstant cable attenuations and a PFLL for data regeneration. The transmitter includes a cable driver which supplies a stable IVpp signal amplitude to the transmission line and a PLL to extract a 310 MHz clock signal.
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