AppliedPRO: process recipe optimizer for R&D acceleration and beyond

Abstract

Semiconductor process development for state-of-the-art devices is a complex task that requires up to years of development. The complexity comes from the need to tune a significant number of process knobs in latest process tools, to meet multiple on-wafer performance targets, across an entire wafer. AppliedPRO® is a software and library of algorithms developed by Applied Materials for process recipe optimization to meet simultaneous process requirements across the entire wafer. The software is tailored to semiconductor use-cases and designed to be primarily used by process engineers to make critical decisions with confidence during process development. Over 100 use-cases have been generated for various semiconductor chips manufacturers, showing faster development time, less development resources, and higher process engineer productivity. This paper shows the use-case of Samsung N+1 Logic BEOL Spacer-Etch process recipe optimization using AppliedPRO®. We utilized AppliedPRO® structured design of experiment methodology and machine-learning algorithms to simultaneously model 10 process-recipe knobs of Applied Materials’ Centris® Sym3® X Etch system and their effect on 8 on-wafer metrics, and determine optimal process knob conditions for minimizing Spacer-tail, which is a key performance metric, while keeping other metrics close to spec. These optimized conditions reduced Spacer-tail by 73% on coupons, which was also validated on full-wafer. These optimal results were previously unachievable in all the previous experimental trials before introducing AppliedPRO®.