An object code compression approach to embedded processors

Abstract

A low-power processor architecture is described dedicatedly for embedded application programs by means of an object code compression approach. This approach unifies duplicated instructions existing in the embedded program and assigns a compressed object code to such an instruction. An instruction decompressor is constructed so as to generate an object code from each compressed object code (pseudo code) input. A single-chip implementation of this decompressor together with a processor core can effectively reduce the bandwidth required for the I/O interface. To demonstrate the practicability of the proposed approach, experiments are applied to an embedded processor ARM610 which attains 62.5% code compression, and hence 42.3% of the power consumption of instruction memory can be reduced.