An RTL methodology to enable low overhead combinational testing

Abstract

This paper introduces a low overhead test methodology, RT-SCAN, applicable to RT Level designs. The methodology enables using combinational test patterns for testing the circuit, as done by traditional full-scan or parallel-scan schemes. However, by exploiting existing connectivity of registers through multiplexors and functional units, RT-SCAN reduces area overhead and test application times significantly compared to full-scan and parallel-scan schemes. Unlike most of the existing high-level test synthesis and test generation schemes which can be most effectively applied to data-flow/arithmetic intensive designs like DSPs and processor designs, the RT-SCAN test scheme can be applied to designs from any application domain, including control-flow intensive designs.