Failure Analysis in a highly parallel processor for Ll Triggering

Abstract

The current paper studies how processor failures affect the dataflow of the Level I Trigger in the BTeV experiment proposed to run at Fermilab's Tevatron. The failure analysis is crucial for a system with over 2500 processing nodes and a number of storage units and communication links of the same order of magnitude. The failure analysis is based on models of the L1 Trigger architecture and shows the dynamics of the architecture's dataflow. The failure analysis provides insight into how system variables are affected by single component failures and provides key information to the implementation Of error recovery strategies. The analysis includes both short term failures from which the system can recover quickly and long term failures which imply a more drastic error recovery strategy. The modeling results are supported by behavioral simulations of the L1 Trigger processing BTeV's Geant Monte Carlo data.