{"title":"A digital-analog mixed temperature compensated crystal oscillator with 1.8V/0.18μm mix-signal CMOS process","authors":"Shulong Li, L. Pan, Liye Wang, Dong Wu","doi":"10.1109/ICIST.2014.6920506","DOIUrl":null,"url":null,"abstract":"In this paper, a digital-analog mixed frequency-temperature compensation method is proposed for high precision temperature compensated crystal oscillators (TCXO). The analog compensation network adopts a temperature sensor and a function generator to generate the cubic and linear analog compensation voltages. The digital compensation network, which contains an 8-bit SAR-ADC, an 8-bit DAC and a 2 Kb CMOS process based non-volatile RAM, is designed to offset the analog compensation deviation and improve the compensation precision with smaller memory capacity. The simulation results show that the proposed approach can achieve 0.2 ppm frequency stability over a wide temperature range from -40°C to 85°C, and the system power consumption is not higher than 1.95mA@1.8V.","PeriodicalId":306383,"journal":{"name":"2014 4th IEEE International Conference on Information Science and Technology","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 4th IEEE International Conference on Information Science and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIST.2014.6920506","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this paper, a digital-analog mixed frequency-temperature compensation method is proposed for high precision temperature compensated crystal oscillators (TCXO). The analog compensation network adopts a temperature sensor and a function generator to generate the cubic and linear analog compensation voltages. The digital compensation network, which contains an 8-bit SAR-ADC, an 8-bit DAC and a 2 Kb CMOS process based non-volatile RAM, is designed to offset the analog compensation deviation and improve the compensation precision with smaller memory capacity. The simulation results show that the proposed approach can achieve 0.2 ppm frequency stability over a wide temperature range from -40°C to 85°C, and the system power consumption is not higher than 1.95mA@1.8V.
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