Mixed signal validation of the Intel/spl reg/ Pentium/spl reg/ 4 microprocessor power-up sequence

Abstract

The design of a robust microprocessor requires extensive logic validation. Millions of test vectors are applied and the output of every logic node is checked against the expected output. This is largely done with RTL simulators. Such simulators ignore the analog aspects of the circuits such as power supply noise and transmission line effects. Traditionally, the analog aspects are taken into account using SPICE-like simulators to model representative cases and design for what is perceived to be the worst-case input stimulus. Alternatively, in this paper, we will present a mixed signal validation approach that comprehends both the logic and analog aspects of the circuits. We show how we applied this to the Pentium 4 processor power-up sequence validation. We will also discuss extending this approach to other disciplines such as platform and packaging.