Investigation of Read Voltage Impact on Foundry BEOL RRAM for Core Integration

Qishen Wang, Zongwei Wang, Lin Bao, Shengyu Bao, Yaotian Ling, Yimao Cai, Ru Huang
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Abstract

In this paper, we investigated the influence of reading conditions on foundry BEOL RRAM characteristics for core transistor integration. The resistance states are statistically analyzed by varying read voltages from 0.05V to 0.4 V with a dedicated test flow to focus on cycle to cycle variation, nonlinearity and switching window. It indicates that optimization of reading voltage should be reviewed by leveraging switching window, read noise, and nonlinearity to obtain better read performance with a limited voltage swing range. This work aims to shed light on the co-impact of several common parameters in RRAM for advanced technology nodes.
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读电压对核心集成铸造BEOL RRAM的影响研究
在本文中,我们研究了读取条件对核心晶体管集成的铸造厂BEOL RRAM特性的影响。通过将读取电压从0.05V变化到0.4 V,通过专门的测试流程来关注周期变化,非线性和开关窗口,对电阻状态进行统计分析。这表明,在有限的电压摆幅范围内,为了获得更好的读性能,应该通过利用开关窗口、读噪声和非线性来优化读电压。这项工作旨在阐明先进技术节点中RRAM中几个常见参数的共同影响。
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