M. Takeuchi, K. Inoue, M. Sakao, T. Sakoh, T. Kitamura, S. Arai, T. Iizuka, T. Yamamoto, H. Shirai, Y. Aoki, M. Hamada, R. Kubota, S. Kishi
{"title":"A 0.15 /spl mu/m logic based embedded DRAM technology featuring 0.425 /spl mu/m/sup 2/ stacked cell using MIM (metal-insulator-metal) capacitor","authors":"M. Takeuchi, K. Inoue, M. Sakao, T. Sakoh, T. Kitamura, S. Arai, T. Iizuka, T. Yamamoto, H. Shirai, Y. Aoki, M. Hamada, R. Kubota, S. Kishi","doi":"10.1109/VLSIT.2001.934931","DOIUrl":null,"url":null,"abstract":"We have developed embedded DRAM technology, in which 0.15 /spl mu/m logic transistor performance is fully compatible with that of pure logic processes. The key technology is the newly developed MIM capacitor element with W-TiN-Ta/sub 2/O/sub 5/-TiN structure. Temperatures as low as 500/spl deg/C are sufficient for the formation process for this MIM capacitor element. Excellent leakage current characteristics of 8/spl times/10/sup -15/ A//spl mu/m/sup 2/ at 125/spl deg/C with T/sub eq/ (equivalent oxide thickness) of 17 /spl Aring/ have been obtained. This technology has been actually implemented into a 4 Mbit test chip with cell size of 0.425 /spl mu/m/sup 2/. Over 50% yield without redundancy was obtained, confirming that there are no basic issues in process integration.","PeriodicalId":232773,"journal":{"name":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2001.934931","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
We have developed embedded DRAM technology, in which 0.15 /spl mu/m logic transistor performance is fully compatible with that of pure logic processes. The key technology is the newly developed MIM capacitor element with W-TiN-Ta/sub 2/O/sub 5/-TiN structure. Temperatures as low as 500/spl deg/C are sufficient for the formation process for this MIM capacitor element. Excellent leakage current characteristics of 8/spl times/10/sup -15/ A//spl mu/m/sup 2/ at 125/spl deg/C with T/sub eq/ (equivalent oxide thickness) of 17 /spl Aring/ have been obtained. This technology has been actually implemented into a 4 Mbit test chip with cell size of 0.425 /spl mu/m/sup 2/. Over 50% yield without redundancy was obtained, confirming that there are no basic issues in process integration.
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