Poly I2L - A high-speed linear compatible structure

R. Davies, J. Meindl
{"title":"Poly I2L - A high-speed linear compatible structure","authors":"R. Davies, J. Meindl","doi":"10.1109/isscc.1977.1155731","DOIUrl":null,"url":null,"abstract":"THE RELATIVELY SLOW SWITCHING speed of 12L fabricated using standard processes for linear integrated circuits limits opportunities for realizing complex, high quality, analog and digital functions on a single monolithic chip. This paper will present a new approach to increase significantly 12L speed ( < l o ns @ 100 pW/gatc), while retaining isolated 15-30 V NPN transistors on 5 G! em epitaxy, without increasing the complexity of the standard linear integrated circuit process.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/isscc.1977.1155731","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

THE RELATIVELY SLOW SWITCHING speed of 12L fabricated using standard processes for linear integrated circuits limits opportunities for realizing complex, high quality, analog and digital functions on a single monolithic chip. This paper will present a new approach to increase significantly 12L speed ( < l o ns @ 100 pW/gatc), while retaining isolated 15-30 V NPN transistors on 5 G! em epitaxy, without increasing the complexity of the standard linear integrated circuit process.
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聚I2L -一种高速线性兼容结构
采用线性集成电路标准工艺制造的12L开关速度相对较慢,限制了在单个单片芯片上实现复杂,高质量,模拟和数字功能的机会。本文将提出一种新方法,以显着提高12L速度(< 0.1 ns @ 100 pW/ gate),同时在5g上保留隔离的15-30 V NPN晶体管!Em外延,不增加标准线性集成电路工艺的复杂性。
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