A 10 /spl mu/V-offset 8 kHz bandwidth 4/sup th/-order chopped /spl Sigma//spl Delta/ A/D converter for battery management

P. Blanken, S. Menten
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引用次数: 7

Abstract

A chopped 4/sup th-/order continuous-time 1 bit /spl Sigma//spl Delta/ A/D converter with 10 /spl mu/V offset and 8 kHz bandwidth has been designed for battery current measurement. Chopping at 16 kHz, the circuit has a 0.1 V input range, a 68 dB SNR, and a 1 MHz output bit rate. Area is 0.45x0.4 mm in 0.35 /spl mu/m CMOS. Current consumption is 30 /spl mu/A at 2.5-4 V.
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用于电池管理的10 /spl mu/ v偏置8 kHz带宽4/sup /阶斩波/spl Sigma//spl Delta/ A/D转换器
设计了一种4/sup /阶连续时间1位/spl σ //spl δ / A/D转换器,偏移量为10 /spl μ /V,带宽为8 kHz,用于电池电流测量。斩波频率为16 kHz,电路的输入范围为0.1 V,信噪比为68 dB,输出比特率为1 MHz。在0.35 /spl mu/m CMOS中,面积为0.45x0.4 mm。在2.5-4 V电压下,电流消耗为30 /spl mu/A。
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Implementation of a third-generation 1.1GHz 64b microprocessor A 0.9 V to 1.95 V dynamic voltage-scalable and frequency-scalable 32 b PowerPC processor A highly-integrated tri-band/quad-mode SiGe BiCMOS RF-to-baseband receiver for wireless CDMA/WCDMA/AMPS applications with GPS capability A low-power RISC microprocessor using dual PLLs in a 0.13 /spl mu/m SOI technology with copper interconnect and low-k BEOL dielectric A 27 mW GPS radio in 0.35 /spl mu/m CMOS
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