Differential DIMM OpenCAPI Memory Interface High Speed Channel Robustness and Scalability Study

Abstract

Differential DIMM (DDIMM) is being defined in JEDEC and uses OMI as a host interface with the data transfer rate being specified at 25.6Gb/s at present and at 51.2Gb/s in the future. A prior 2019∼20 study [13] of full channel simulation and electrical test with initial DDR4 DDIMM engineering samples demonstrated the feasibility to achieve BER 10^-15 at 25.6Gb/s OMI bus data rate. In this study, the test result in production environment with much larger DDR4 DDIMM sample size will be analyzed for 25.6Gb/s OMI channel robustness. In addition, this study will explore the OMI bus data rate scale to 32Gb/s with the full channel time domain eye diagram analysis with BER at 10^-15. The prior studies in 2018∼20 [1], [13] concluded that the typical Copper Clad Laminate (CCL) and prepreg material used in the industry standard U/R/LR DIMM leads to signal integrity degradation relative to a better reference material at 25.6Gb/s OMI bus data rate while the improved DDIMM PCB stack-up with hybrid laminate material set has shown adequate margin. The DDIMM PCB stack-ups of this study include this hybrid material as baseline and lower loss Megtron 6 like material sets. DDIMM will be paired with the Storage Networking Industry Association (SNIA) SFF-TA-1002 high speed connector. The signal integrity challenges of DDIMM PCB contact interface to SFF-TA-1002 connector have been highlighted in the prior studies in 2018∼20[1], [13]. This study will discuss the contact interface robustness. In summary, this paper will present DDR4 DDIMM 25.6Gb/s OMI channel robustness study and the OMI channel scalability study to 32Gb/s which is planned for DDR5 DDIMM at product launch.