False path detection at transistor level

Abstract

The prevalent concern over static timing analysis is that it might produce a very pessimistic result in presence of false paths in the circuit. It is therefore essential to detect and avoid the false paths during timing analysis, to estimate the timing characteristics of the design better. In this paper a framework is presented to automatically detect false paths at the transistor level. The false path detection involves logic extraction from a transistor level netlist and then detecting false paths, with more accurate estimation of the path delays.