{"title":"Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations","authors":"N. Mojumder, S. Gupta, K. Roy","doi":"10.1109/DRC.2011.5994466","DOIUrl":null,"url":null,"abstract":"We propose a three terminal, dual pillar magnetic tunnel junction (MTJ) with tilted magnetic anisotropy for fast and error-free precessional magnetic switching with near-disturb-free magneto-resistive data sensing. Marginal tilting of magnetic anisotropy of the pinned layer in the write-in port enables fast (∼2ns) and error-free magnetic switching, subject to an electric current density of almost 70% lower than that required in a conventional STT-MRAM with perpendicular magnetic anisotropy (PMA). A thicker tunnel barrier is incorporated in the spatially and electrically isolated read-out port for higher tunneling magneto-resistance (TMR) and near-disturb-free read operations. Dual bit line memory architecture with just one access transistor per bit-cell is also proposed. The technology-circuit co-optimization of the proposed one transistor Dual Pillar Spin Transfer Torque (DPSTT) MRAM cell is carried out using effective mass-based spin transport [1] and finite temperature macro-magnetic simulations involving Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation [2–4]. The proposed DPSTT-MRAM bit-cell outperforms the state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell TMR, single supply voltage for read/write, near-disturb-free data access under parametric process variations with comparable or even lower critical switching current.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"69th Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2011.5994466","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
We propose a three terminal, dual pillar magnetic tunnel junction (MTJ) with tilted magnetic anisotropy for fast and error-free precessional magnetic switching with near-disturb-free magneto-resistive data sensing. Marginal tilting of magnetic anisotropy of the pinned layer in the write-in port enables fast (∼2ns) and error-free magnetic switching, subject to an electric current density of almost 70% lower than that required in a conventional STT-MRAM with perpendicular magnetic anisotropy (PMA). A thicker tunnel barrier is incorporated in the spatially and electrically isolated read-out port for higher tunneling magneto-resistance (TMR) and near-disturb-free read operations. Dual bit line memory architecture with just one access transistor per bit-cell is also proposed. The technology-circuit co-optimization of the proposed one transistor Dual Pillar Spin Transfer Torque (DPSTT) MRAM cell is carried out using effective mass-based spin transport [1] and finite temperature macro-magnetic simulations involving Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation [2–4]. The proposed DPSTT-MRAM bit-cell outperforms the state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell TMR, single supply voltage for read/write, near-disturb-free data access under parametric process variations with comparable or even lower critical switching current.