{"title":"State machine abstraction from circuit layouts using BDDs: applications in verification and synthesis","authors":"T. Kam, P. Subrahmanyam","doi":"10.1109/EURDAC.1992.246259","DOIUrl":null,"url":null,"abstract":"The authors discuss a formal technique for abstracting a finite state machine (FSM) from a transistor netlist, given information relating to clock signals and clo.cking methodology. The abstracted FSM is represented as a transition relation using binary decision diagrams (BDDs) and then converted into a synchronous sequential network. Both the relational and network representations are common starting points for various sequential synthesis and verification tools.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings EURO-DAC '92: European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1992.246259","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
The authors discuss a formal technique for abstracting a finite state machine (FSM) from a transistor netlist, given information relating to clock signals and clo.cking methodology. The abstracted FSM is represented as a transition relation using binary decision diagrams (BDDs) and then converted into a synchronous sequential network. Both the relational and network representations are common starting points for various sequential synthesis and verification tools.<>
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