A V-band Power Amplifier for Satellite Communications in 40-nm CMOS

Abstract

This paper presents a V-band power amplifier (PA) with two stages. Each stage consists of a neutralized common-source amplifier pair, coupled with each other using a transformer. Implemented in 40-nm CMOS technology, the proposed two-stage PA achieves a measured small-signal gain of 16.8 dB at 47 GHz with a 3-dB bandwidth more than 6.5 GHz. The maximum 1-dB compressed output power (P1dB) is 12.2 dBm with a power-added efficiency at P1dB (PAE1dB) of 18% measured at 47 GHz; from 45 to 51 GHz, the measured P1dBis above 10 dBm under a 1.1-V supply voltage.