Shaping a VLSI wire to minimize Elmore delay

Abstract

Euler's differential equation of the calculus of variations is used to determine the shape of a VLSI wire that minimizes Elmore delay. The solution is given as a power series whose coefficients are formulas involving the load-end wire width, the load capacitance, the capacitance per unit area, and the capacitance per unit perimeter. In contrast to an optimal-width rectangular wire, the RC Elmore delay of the optimally tapered wire goes to zero as the driver resistance goes to zero. The optimal taper is immune, to first order, to process variations affecting wire width.