Reverse-bias stability and reliability of hole-barrier-free E-mode LPCVD-SiNx/GaN MIS-FETs

Abstract

With substantially limited holes generation, the E-mode n-channel LPCVD-SiNx/GaN MIS-FET delivers small NBTI (with Vds = 0 V and a negative Vgs = −30 V) even without a hole-barrier. In high reverse-bias (i.e. high drain bias off-state with Vgs < Vth and large Vds) stress, larger negative gate-bias is found to accelerate positive shift in Vth, suggesting a hole-induced gate dielectric degradation mechanism. It is also revealed that the hole-induced dielectric breakdown can be greatly contained when Vgs is limited to a few volts below Vth.