High Temperature Data Retention of Ferroelectric Memory on 130nm and 180nm CMOS

Abstract

Systematic evaluation of ferroelectric memory (FRAM) data retention mechanisms under high temperature exposure are reported. The FRAM devices are embedded on ultra-low power, analog-enhanced 130nm and 180nm CMOS technologies. Capability of the FRAM to retain data through 260°C Pb-free solder assembly reflow is demonstrated. The 130nm FRAM is shown to achieve the equivalent of 10 years data retention at 125°C, with intrinsic margin comparable to the 180nm FRAM, previously shown to achieve 10 years at 125°C retention.