Bijoy Goswami, Debadipta Basak, A. Bhattacharya, Koelgeet Kaur, Sutanni Bhowmick, S. Sarkar
{"title":"Analytical Modeling and Simulation of Low Power Salient Source Double Gate TFET","authors":"Bijoy Goswami, Debadipta Basak, A. Bhattacharya, Koelgeet Kaur, Sutanni Bhowmick, S. Sarkar","doi":"10.1109/DEVIC.2019.8783677","DOIUrl":null,"url":null,"abstract":"The analytical surface potential model of 22nm salient source Double Gate TFET (SS-DG-TFET) is presented in this paper. The surface potential is analyzed as the performance parameter along with an assessment of improved ON/ OFF current ratio. The variation of tunnel current is examined under same front and back gate bias together with identical oxide thickness. The source region has been extended symmetrically in both directions in order to enhance the conductivity of the channel region and it has been efficiently deployed in the proposed model. The execution of low power functionality and lower sub-threshold slope is also established in this model. The analytical results have been suitably validated using Silvaco, Atlas.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Devices for Integrated Circuit (DevIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DEVIC.2019.8783677","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The analytical surface potential model of 22nm salient source Double Gate TFET (SS-DG-TFET) is presented in this paper. The surface potential is analyzed as the performance parameter along with an assessment of improved ON/ OFF current ratio. The variation of tunnel current is examined under same front and back gate bias together with identical oxide thickness. The source region has been extended symmetrically in both directions in order to enhance the conductivity of the channel region and it has been efficiently deployed in the proposed model. The execution of low power functionality and lower sub-threshold slope is also established in this model. The analytical results have been suitably validated using Silvaco, Atlas.
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