Design and Implementation of 32 bit MIPS based RISC Processor

Abstract

MIPS-based RISC processor has a wide range of applications because of its low power consumption and high-speed performance. Here a design of Pipeline based MIPS processor is proposed using the forwarding and stalling process. A pipeline is used to improve each stage’s utilization factor and improve the overall performance of MIPS. A pipeline-based MIPS processor is presented here and has different five processing stages instruction fetch (IF), instruction decode (ID), execution (EXE), memory (MEM), and write back(WB). The data hazard solving technique is achieved by using the method as mentioned above. The design had been synthesized and simulated with the help of the Xilinx Vivado tool and implemented in the Virtex ultra scale board, and the total consumption power of 0.999 W is measured.