Improving diagnostic resolution of delay faults in FPGAs by exploiting reconfigurability

Abstract

Given an FPGA that has failed to meet its timing specification, techniques are proposed to efficiently diagnose the cause of the faulty behavior. An initial list of suspect configuration logic blocks (CLBs) and interconnects is generated using six-valued fault-free simulation and critical path tracing. The initial list of suspects is then reduced by exploiting the reconfigurability of an FPGA. Experimental results indicate a dramatic reduction in the size of the suspect list.