Digital Defect Based Built-in Self-Test for Low Dropout Voltage Regulators

Mehmet Ince, S. Ozev
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引用次数: 5

Abstract

With the increasing complexity of electronic components in critical applications, pressure on single components to have zero defects is also increasing. Thus there is a need to explore built-in self-test and other non-traditional test techniques for mixed-signal circuits, such as data converters, phase locked loops and power converters. In this paper, we present an extremely low cost, digital built-in self-test methodology for Low Dropout Regulators (LDO), specifically used for defect detection. The technique relies on perturbing the LDO loop at the reference voltage input via pseudo random binary sequence which has white noise characteristics and cross correlating the output of LDO with input excitation using only digital circuits, thus inducing low power and area overhead. The built-in self-test technique together with an LDO is designed using 65nm TMSC technology. Transistor level structural fault simulations display that all inserted faults can be detected even if they do not change the DC level of the LDO output.
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基于数字缺陷的低降稳压器内置自检
随着关键应用中电子元件的复杂性日益增加,单个元件零缺陷的压力也在增加。因此,有必要探索混合信号电路的内置自检和其他非传统测试技术,如数据转换器、锁相环和功率转换器。在本文中,我们提出了一种极低成本的数字内置自检方法,用于低差稳压器(LDO),专门用于缺陷检测。该技术依赖于通过具有白噪声特性的伪随机二进制序列在参考电压输入处扰动LDO环路,并且仅使用数字电路将LDO输出与输入激励交叉相关,从而产生低功耗和面积开销。内置自检技术和LDO采用65nm TMSC技术设计。晶体管级结构故障模拟显示,即使没有改变LDO输出的直流电平,也可以检测到所有插入的故障。
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